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ltc1876 1 1876fa applicatio s u features descriptio u typical applicatio u high efficiency, 2-phase, dual synchronous step-down switching controller and step-up regulator the ltc ? 1876 is a high performance triple output switching regulator. it incorporates a dual step-down switching con- troller that drives all n-channel synchronous power mosfet stages. a step-up regulator with an internal 1a, 36v switch provides the third output. the step-down controllers minimize power loss and noise by operating the output stage of each controller out of phase. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. a run/ss pin for each controller provides both soft-start and an optional timed, short-circuit shutdown that can be configured to latch off one or both controllers. current foldback provides additional short-circuit protection. in an overvoltage condition, the bottom mosfet is latched on until v out returns to normal. the fcb pin can be used to inhibit burst mode operation or to enable regulation of a secondary output voltage. the step-up regulator operates at 1.2mhz, allowing the use of tiny low cost capacitors and inductors. in addition, its internal 1a switch allows high current outputs to be generated. its current mode control scheme provides excellent line and load regulation. step-down controller n out-of-phase controllers reduce required input capacitance and power supply induced noise n power good output voltage indicator n opti-loop tm compensation minimizes c out n dc programmed fixed frequency 150khz to 300khz n wide v in range: 3.5v to 36v operation n very low dropout operation: 99% duty cycle n adjustable soft-start current ramping n latched short-circuit shutdown with defeat option n remote output voltage sense and ov protection n 5v and 3.3v standby regulators n selectable const. freq. or burst mode tm operation step-up regulator n high operating switching frequency of 1.2mhz n low internal v cesat switch: 400mv @ 1a, v in = 3v n wide v in range: 2.6v to 16v operation n high output voltage: up to 34v n 3.3v input step-down converter n notebook and palmtop computers, pdas n battery-operated digital devices , ltc and lt are registered trademarks of linear technology corporation. burst mode and opti-loop are trademarks of linear technology corporation. figure 1. high efficiency triple 5v/3.3v/12v power supply 4.7 f 10v m4 m3 0.1 f 63.4k 1% 1000pf 6.3 h 220pf 1 f cer 33 f 35v alum 10 f 35v cer + 56 f 4v sp 0.01 20k 1% 15k v out2 3.3v 5a m2 m1 0.1 f 105k 1% 6.8 h 220pf 1000pf + + + + 47 f 6.3v sp 0.01 20k 1% 10.2k 1% 15k v out1 5v 4a v out3 12v 200ma tg2 tg1 boost2 boost1 sw2 sw1 bg2 bg1 pgnd pgood auxsw auxv fb auxsd sense2 + sense1 + sense2 sense1 v osense2 v osense1 i th2 i th1 auxv in v in intv cc run/ss2 run/ss1 v in 5.2v to 28v m1, m2, m3, m4: fds6680a 1876 ta01 0.1 f 0.1 f ltc1876 sgnd 86.6k, 1% 10 h 10 f 20v
ltc1876 2 1876fa symbol parameter conditions min typ max units main control loops v osense1, 2 regulated feedback voltage i th1, 2 voltage = 1.2v (note 4) l 0.792 0.800 0.808 v i vosense1, 2 feedback current (note 4) C5 C50 na v reflnreg reference voltage line regulation v in = 3.6v to 30v (note 4) 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop; d i th voltage = 1.2v to 0.7v l 0.1 0.5 % measured in servo loop; d i th voltage = 1.2v to 2v l C0.1 C0.5 % g m1, 2 transconductance amplifier g m i th1, 2 = 1.2v; sink/source 5 m a; (note 4) 1.3 mmho g mol1, 2 transconductance amplifier gbw i th1, 2 = 1.2v; (note 4) 3 mhz i q input dc supply current (note 5) normal mode v in = 15v; extv cc tied to v out1 ; v out1 = 5v 350 m a standby v run/ss1, 2 = 0v, v stbymd > 2v 125 m a shutdown v run/ss1, 2 = 0v, v stbymd = open 20 35 m a v fcb forced continuous threshold l 0.76 0.800 0.84 v i fcb forced continuous current v fcb = 0.85v C0.3 C0.18 C0.1 m a v binhibit burst inhibit (constant frequency) measured at fcb pin 4.3 4.8 v threshold input supply voltage (v in )......................... 36v to C0.3v topside driver voltages (boost1, boost2) ................................... 42v to C0.3v switch voltage (sw1, sw2) ......................... 36v to C5v intv cc, extv cc , run/ss1, run/ss2, pgood, (boost1-sw1), (boost2-sw2), ...............7v to C 0.3v sense1 + , sense2 + , sense1 C , sense2 C voltages ................................... (1.1)intv cc to C 0.3v freqset, stbymd, fcb, pgood voltages ..................................................7v to C 0.3v i th1, i th2 , v osense1 , v osense2 voltages ... 2.7v to C0.3v peak output current <10 m s (tg1, tg2, bg1, bg2) ... 3a intv cc peak output current ................................ 50ma auxv in .................................................................. 16v to C0.3v auxsd ..................................................................... 10v auxsw ..................................................... 36v to C0.3v auxv fb voltage ....................................... 2.5v to C0.3v current into auxv fb ....................................................... 1ma operating temperature range (note 2) ...C40 c to 85 c junction temperature (note 3) ............................. 125 c storage temperature range ..................C65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, q ja = 95 c/w consult factory for parts specified with wider operating temperature ranges. ltc1876eg absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss1, 2 = 5v, auxv in = 3v unless otherwise noted. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 auxsd auxv in auxpgnd auxpgnd run/ss1 sense1 + sense1 v osense1 freqset stbymd fcb i th1 sgnd 3.3v out i ith2 v osense2 sense2 sense2 + auxsgnd auxv fb auxsw auxsw
ltc1876 3 1876fa symbol parameter conditions min typ max units uvlo undervoltage lockout v in ramping down l 3.5 4 v v ovl overvoltage feedback threshold measured at v osense1, 2 l 0.84 0.86 0.88 v i sense sense pins total source current (each channel); v sense1 C , 2 C = v sense1 + , 2 + = 0v C85 C60 m a v stbymd ms master shutdown threshold v stbymd ramping down 0.4 0.6 v v stbymd ka keep-alive power on-threshold v stbymd ramping up, run ss1, 2 = 0v 1.5 2 v df max maximum duty factor in dropout 98 99.4 % i run/ss1, 2 soft-start charge current v run/ss1, 2 = 1.9v 0.5 1.2 m a v run/ss1, 2 on run/ss pin on threshold v run/ss1, v run/ss2 rising 1.0 1.5 1.9 v v run/ss1, 2 lt run/ss pin latchoff arming threshold v run/ss1, v run/ss2 rising from 3v 4.1 4.5 v i scl1, 2 run/ss discharge current soft short condition v osense1, 2 = 0.5v; 0.5 2 4 m a v run/ss1, 2 = 4.5v i sdlho shutdown latch disable current v osense1, 2 =0.5v 1.6 5 m a v sense(max) maximum current sense threshold v osense1, 2 = 0.7v , v sense1 C , 2 C = 5v l 62 75 88 mv tg transition time: tg1, 2 t r rise time c load = 3300pf 50 90 ns tg1, 2 t f fall time c load = 3300pf 50 90 ns bg transition time: bg1, 2 t r rise time c load = 3300pf 40 90 ns bg1, 2 t f fall time c load = 3300pf 40 80 ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver 90 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver 90 ns t on(min) minimum on-time tested with a square wave (note 7) 180 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v 4.8 5.0 5.2 v v ldo int intv cc load regulation i cc = 0 to 20ma, v extvcc = 4v 0.2 1.0 % v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 80 160 mv v extvcc extv cc switchover voltage i cc = 20ma, extv cc ramping positive l 4.5 4.7 v v ldohys extv cc hysteresis 0.2 v oscillator f osc oscillator frequency v freqset = open (note 8) 190 220 250 khz f low lowest frequency v freqset = 0v 120 140 160 khz f high highest frequency v freqset = 2.4v 280 310 360 khz i freqset freqset input current v freqset = 2.4v C2 C1 m a electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss1, 2 = 5v, auxv in = 3v unless otherwise noted.
ltc1876 4 1876fa symbol parameter conditions min typ max units 3.3v linear regulator v 3.3out 3.3v regulator output voltage no load l 3.25 3.35 3.45 v v 3.3il 3.3v regulator load regulation i 3.3 = 0ma to 10ma 0.5 2 % v 3.3vl 3.3v regulator line regulation 6v < v in < 30v 0.05 0.2 % pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 1 m a v pg pgood trip level, either controller v osense with respect to set output voltage v osense ramping negative C6 C7.5 C9.5 % v osense ramping positive 6 7.5 9.5 % aux output auxv inmin aux minimum operating voltage l 2.4 2.6 v auxv fb aux regulated feedback voltage l 1.23 1.26 1.28 v auxi fb aux feedback pin bias current l 120 360 na auxi q aux input dc supply current normal mode v auxsd = 2.4v, not switching 4 ma shutdown v auxsd = 0v 0.01 1 m a auxv linereg aux line regulation 2.6v auxv in 16v 0.01 0.05 %/v auxf osc aux oscillator frequency l 0.8 1.2 1.6 mhz auxdc max aux oscillator maximum duty cycle l 84 86 % auxi limit aux switch current limit (note 9) 1 1.4 2 a auxv cesat aux switch saturation voltage i sw = 900ma (note 10) 330 550 mv auxi leakage aux switch leakage current v sw = 5v 0.01 1 m a auxv auxsd aux shutdown input voltage aux shutdown upper trip point 2.4 v aux shutdown lower trip point 0.5 v i auxsd auxsd pin bias current v auxsd = 3v 16 32 m a v auxsd = 0v 0.01 0.1 m a note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc1876e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc1876eg: t j = t a + (p d ? 95 c/w) note 4: the ltc1876 is tested in a feedback loop that servos v ith1, 2 to a specified voltage and measures the resultant v osense1, 2. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is specified for an inductor peak- to-peak ripple current 3 40% of i max (see minimum on-time considerations in the applications information section). note 8: v freqset pin internally tied to 1.19v reference through a large resistance. note 9 : current limit guaranteed by design and/or correlation to static test. note 10 : 100% tested at wafer level. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss1, 2 = 5v, auxv in = 3v unless otherwise noted.
ltc1876 5 1876fa typical perfor a ce characteristics uw output current (a) 0.001 0 efficiency (%) 10 30 40 50 100 70 0.01 0.1 1 1876 g01 20 80 90 60 10 forced continuous mode constant frequency (burst disable) burst mode operation v in = 15v v out = 5v output current (a) 0.001 efficiency (%) 70 80 10 1876 g02 60 50 0.01 0.1 1 100 90 v in = 10v v in = 15v v in = 7v v in = 20v v out = 5v input voltage (v) 5 efficiency (%) 70 80 1876 g03 60 50 15 25 35 100 v out = 5v i out = 3a 90 efficiency vs output current and mode (figure 1) input voltage (v) 05 0 supply current ( a) 400 1000 10 20 25 1876 g04 200 800 600 15 30 35 both controllers on standby shutdown current (ma) 0 extv cc voltage drop (mv) 150 200 250 40 1876 g05 100 50 0 10 20 30 50 temperature ( c) ?0 intv cc and extv cc switch voltage (v) 4.95 5.00 5.05 25 75 1876 g06 4.90 4.85 ?5 0 50 100 125 4.80 4.70 4.75 intv cc voltage extv cc switchover threshold input voltage (v) 0 4.8 4.9 5.1 15 25 1876 g07 4.7 4.6 510 20 30 35 4.5 4.4 5.0 intv cc voltage (v) i load = 1ma internal 5v ldo line regulation v in supply current vs input voltage and mode (figure 1) duty factor (%) 0 0 v sense (mv) 25 50 75 20 40 60 80 1876 g08 100 percent on nominal output voltage (%) 0 v sense (mv) 40 50 60 100 1876 g09 30 20 0 25 50 75 10 80 70 efficiency vs output current (figure 1) efficiency vs input voltage (figure 1) extv cc voltage drop intv cc and extv cc switch voltage vs temperature maximum current sense threshold vs duty factor maximum current sense threshold vs percent of nominal output voltage (foldback)
ltc1876 6 1876fa typical perfor a ce characteristics uw v run/ss (v) 0 0 v sense (mv) 20 40 60 80 1234 1876 g10 56 v sense(cm) = 1.6v common mode voltage (v) 0 v sense (mv) 72 76 80 4 1876 g11 68 64 60 1 2 3 5 v ith (v) 0 v sense (mv) 30 50 70 90 2 1876 g12 10 ?0 20 40 60 80 0 ?0 ?0 0.5 1 1.5 2.5 load current (a) 0 normalized v out (%) 0.2 0.1 4 1876 g13 0.3 0.4 1 2 3 5 0.0 fcb = 0v v in = 15v figure 1 v run/ss (v) 0 0 v ith (v) 0.5 1.0 1.5 2.0 2.5 1 234 1876 g14 56 v osense = 0.7v v sense common mode voltage (v) 0 i sense ( a) 0 1876 g15 ?0 100 24 50 100 6 temperature ( c) 50 ?5 70 v sense (mv) 74 80 0 50 75 1876 g16 72 78 76 25 100 125 temperature ( c) ?0 25 0 run/ss current ( a) 0.2 0.6 0.8 1.0 75 100 50 1.8 1876 g18 0.4 0 25 125 1.2 1.4 1.6 maximum current sense threshold vs v run/ss (soft-start) maximum current sense threshold vs sense common mode voltage current sense threshold vs i th voltage load regulation (controller) v ith vs v run/ss sense pins total source current maximum current sense threshold vs temperature current sense pin input current vs temperature run/ss current vs temperature temperature ( c) 50 ?5 25 current sense input current ( a) 27 35 0 50 75 1876 g17 31 33 29 25 100 125 v out = 5v
ltc1876 7 1876fa temperature ( c) ?0 25 0 extv cc switch resistance ( ) 4 10 0 50 75 1876 g19 2 8 6 25 100 125 temperature ( c) ?0 200 250 350 25 75 1876 g20 150 100 ?5 0 50 100 125 50 0 300 frequency (khz) v freqset = 5v v freqset = open v freqset = 0v temperature ( c) ?0 undervoltage lockout (v) 3.40 3.45 3.50 25 75 1876 g21 3.35 3.30 ?5 0 50 100 125 3.25 3.20 temperature ( c) ?0 25 0 shutdown latch thresholds (v) 0.5 1.5 2.0 2.5 75 100 50 4.5 1876 g22 1.0 0 25 125 3.0 3.5 4.0 latch arming latchoff threshold shutdown pin voltage (v) 0 shutdown pin current ( a) 15 20 25 3 5 1876 g23 10 5 0 12 4 30 35 40 6 t a = 25 c t a = 100 c temperature ( c) ?0 3.6 quiescent current (ma) 3.8 3.9 4.0 4.1 4.2 4.3 0 50 1876 g24 4.4 4.5 4.6 3.7 100 v in = 5v v fb = 1.3v not switching v in = 3.3v temperature ( c) ?0 1.22 feedback voltage (v) 1.23 1.24 1.25 1.26 1.28 ?5 02550 1876 g25 75 100 1.27 typical perfor a ce characteristics uw extv cc and switch resistance vs temperature undervoltage lockout vs temperature (controller) oscillator frequency vs temperature (controller) shutdown latch thresholds vs temperature shutdown pin current (i auxvfb ) quiescent current for auxillary regulator feedback pin voltage (auxv fb ) current limit for auxillary regulator auxillary regulator switch oscillator frequency temperature ( c) ?0 30 ?0 1.05 frequency (mhz) 1.10 1.15 1.20 1.25 1.35 10 30 50 70 90 110 1876 g28 1.30 duty cycle (%) 10 current li mit (a) 0.8 1.2 90 1876 g26 0.4 0 30 50 70 20 40 60 80 1.6 0.6 1.0 0.2 1.4
ltc1876 8 1876fa run/ss1, run/ss2 (pins 1, 23): combination of soft-start, run control inputs and short-circuit detection timers. a capacitor to ground at each of these pins sets the ramp time to full output current. forcing either of these pins back below 1v causes the ic to shut down the circuitry required for that particular controller. latchoff overcurrent protection is also invoked via this pin as described in the applications informa- tion section. sense1 + , sense2 + (pins 2, 14): the (+) input to each differential current comparator. the i th pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold. sense1 C , sense2 C (pins 3, 13): the (C) input to the differential current comparators. v osense1 , v osense2 (pins 4, 12): receives the remotely- sensed feedback voltage for each controller from an external resistive divider across the output. freqset (pin 5): frequency control input to the oscillator. this pin can be left open, tied to ground, tied to intv cc or driven by an external voltage source. this pin can also be used with an external phase detector to build a true phase-locked loop. stbymd (pin 6): control pin that determines which circuitry remains active when the controllers are shut down and/or typical perfor a ce characteristics uw pi n fu n ctio n s uuu v in = 15v v out = 5v load step = 0a to 3a burst mode operation 20 m s/div 1876 g30 v out 200mv/div i out 2a/div load step (figure 1) constant frequency (burst inhibit) operation (figure 1) input source/capacitor instantaneous current (figure 1) burst mode operation (figure 1) i in 2a/div v in 200mv/div v sw2 10v/div v in = 15v v out = 5v i out5 = i out3.3 = 2a 1 m s/div 1876 g31 v sw1 10v/div v out 20mv/div i out 0.5a/div v in = 15v v out = 5v v fcb = open i out = 20ma 10 m s/div 1876 g32 v out 20mv/div i out 0.5a/div v in = 15v v out = 5v v fcb = 5v i out = 20ma 2 m s/div 1876 g33 v in = 15v v out = 5v load step = 0a to 3a continuous mode load step (figure 1) v out 200mv/div i out 2a/div
ltc1876 9 1876fa provides a common control point to shut down both control- lers. see the operation section for details. fcb (pin 7): forced continuous control input. this input acts on both controllers and is normally used to regulate a secondary winding. pulling this pin below 0.8v will force continuous synchronous operation on both controllers. do not leave this pin floating. i th1, i th2 (pins 8, 11): error amplifier output and switching regulator compensation point. each associated channels current comparator trip point increases with this control voltage. sgnd (pin 9): small signal ground common to both control- lers, must be routed separately from high current grounds to the common (C) terminals of the c out capacitors. 3.3v out (pin 10): output of a linear regulator capable of supplying up to 10ma dc with peak currents as high as 50ma. auxsgnd (pin 15): small signal ground of the auxiliary boost regulator. auxv fb (pin 16): auxiliary boost regulator feedback volt- age. this pin receives the feedback voltage from an external resistive divider across the auxiliary output. auxsw (pins 17, 18): switch node connections to inductor for the auxiliary regulator. voltage swing at these pins are from ground to (v out + voltage across shottky diode). minimize trace area at these pins to keep emi down. auxpgnd (pins 19, 20): the auxiliary power ground pins. its gate drive currents are returned to these pin. auxv in (pin 21): auxiliary boost regulator controller sup- ply pin. must be closely decoupled to auxpgnd. auxsd (pin 22): shutdown pin for the auxiliary regulator. connect to 2.4v or more to enable the auxiliary regulator or ground to shut the auxiliary regulator off. tg1, tg2 (pins 35, 24): high current gate drives for top n-channel mosfets. these are the outputs of floating drivers with a voltage swing equal to intv cc C 0.5v superim- posed on the switch node voltage sw. sw1, sw2 (pins 34, 25): switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . boost1, boost2 (pins 33, 26): bootstrapped supplies to the top side floating drivers. capacitors are connected between the boost and switch pins and schottky diodes are tied between the boost and intv cc pins. voltage swing at the boost pins is from intv cc to (v in + intv cc ). bg1, bg2 (pins 31, 27): high current gate drives for bottom (synchronous) n-channel mosfets. voltage swing at these pins is from ground to intv cc . pgnd (pin 28): driver power ground. connects to sources of bottom (synchronous) n-channel mosfets, anode of the schottky rectifier and the (C) terminal(s) of c in . intv cc (pin 29): output of the internal 5v linear low dropout regulator and the extv cc switch. the driver and control circuits are powered from this voltage source. must be decoupled to power ground with a minimum of 4.7 m f tantalum or other, low esr capacitor. the intv cc regulator standby operation is determined by the stbymd pin. extv cc (pin 30): external power input to an internal switch connected to intv cc . this switch closes and supplies v cc power, bypassing the internal low dropout regulator, when- ever extv cc is higher than 4.7v. see extv cc connection in applications section. do not exceed 7v on this pin . v in (pin 32): main supply pin. a bypass capacitor should be tied between this pin and the signal ground pin. pgood (pin 36): open-drain logic output. pgood is pulled to ground when the voltage on either v osense pin is not within 7.5% of its setpoint. pi n fu n ctio n s uuu
ltc1876 10 1876fa fu n ctio n al diagra uu w switch logic + 0.8v 4.8v 5v v in v in 4.5v binh v osense1 v osense2 clk2 clk1 0.18 a r6 r5 + + + + fcb + + + + v ref window comparator internal supply 3.3v out v sec fcb pgood extv cc intv cc sgnd stbymd + + 5v ldo reg sw shdn 0.55v top boost tg c b c in d 1 d b pgnd bot bg intv cc intv cc v in + c sec c out v out 1876 fd/f02 d sec r sense r2 + v osense drop out det run soft start bot top on s r q q s q q oscillator freqset fcb ea 0.86v 0.80v ov v fb 1.2 a 6v r1 + r c 4(v fb ) rst shdn run/ss i th c c c c2 c ss 1.19v 1m + 4(v fb ) 0.86v slope comp 3mv + + sense sense + intv cc 30k 45k 2.4v 45k 30k i1 i2 b duplicate for second controller channel + + run/ss1 1.26v v ref c c r c s ramp generator 1.2mhz oscillator osc aux ea aux a1 aux r r7 r8 auxsw auxsd d5 l3 auxv fb auxv out auxv in c outaux auxpgnd boost regulator figure 2
ltc1876 11 1876fa main control loop the ltc1876 uses a constant frequency, current mode scheme to provide excellent line and load regulation for all its outputs. the step-down controllers have two of its switch drivers operating at 180 degrees out of phase from each other. during normal operation, each top mosfet is turned on when the clock for that channel sets the r s latch, and turned off when the main current comparator, i1, resets the r s latch. the peak inductor current at which i1 resets the r s latch is controlled by the voltage on the i th pin, which is the output of each error amplifier ea. the v osense pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current increases, it causes a slight de- crease in v osense relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current comparator i2, or the beginning of the next cycle. the top mosfet drivers are biased from floating boot- strap capacitor c b , which normally is recharged during each off cycle through an external diode when the top mosfet turns off. as v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector de- tects this and forces the top mosfet off for about 500ns every tenth cycle to allow c b to recharge. the main control loop is shut down by pulling the run/ss pin low. releasing run/ss allows an internal 1.2 m a current source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, the i th pin voltage is gradually released allowing normal, full-current opera- tion. when both run/ss1 and run/ss2 are low, all ltc1876 controller functions are shut down, and the stbymd pin determines if the standby 5v and 3.3v regulators are kept alive. aux regulator the auxiliary boost regulator is completely independent from other ltc1876 circuits. it can be operated even though the ltc1876 step-down controllers are in shut- down. the operation of the boost regulator is similar to the controllers. the oscillator, osc aux , sets the r s latch and turns on the monolithic power switch. a voltage propor- tional to the switch current is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the pwm comparator, a1 aux . when this voltage exceeds the level at the negative input of a1 aux , the sr latch is reset, turning off the power switch. the level at the negative input of a1 aux is set by the error amplifier ea aux and is simply an amplified version of the difference between the feed- back voltage and the reference voltage. hence the error amplifier sets the correct peak current level to keep the output in regulation. to protect the power switch from excessive current, a 1a minimum limit is internally set. when the switch reaches this limit, it will force the latch to reset, turning it off. applying a voltage less than 0.5v on the shutdown pin will put the boost regulator in shutdown. low current operation the fcb pin is a multifunction pin providing two functions: 1) to provide regulation for a secondary winding by temporarily forcing continuous pwm operation on both controllers; and 2) select between two modes of low current operation. when the fcb pin voltage is below 0.8v, the controller forces continuous pwm current operation. in this mode, the top and bottom mosfets are alternately turned on to maintain the output voltage independent of direction of inductor current. when the fcb pin is below v intvcc C 2v but greater than 0.8v, the controller enters burst mode operation. burst mode operation sets a mini- mum output current level before turning off the top switch and turns off the synchronous mosfet(s) when the inductor current goes negative. this combination of re- quirements will, at low currents, force the i th pin below a voltage threshold that will temporarily inhibit turn-on of both output mosfets until the output voltage drops slightly. there is 60mv of hysteresis in the burst compara- tor b tied to the i th pin. this hysteresis produces output signals to the mosfets that turn them on for several (refer to functional diagram) operatio u
ltc1876 12 1876fa cycles, followed by a variable sleep interval depending upon the load current. the resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. constant frequency operation when the fcb pin is tied to intv cc , burst mode operation is disabled and the forced minimum output current re- quirement is removed. this provides constant frequency, discontinuous (preventing reverse inductor current) cur- rent operation over the widest possible output current range. this constant frequency operation is not as efficient as burst mode operation, but does provide a lower noise, constant frequency operating mode down to approxi- mately 1% of designed maximum output current. constant current (pwm) operation tying the fcb pin to ground will force continuous current operation. this is the least efficient operating mode, but may be desirable in certain applications. the output can source or sink current in this mode. when sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boost- ing the input supply to dangerous voltage levels beware! frequency setting the freqset pin provides frequency adjustment to the controllers internal oscillator from approximately 140khz to 310khz. this input is nominally biased through an internal resistor to the 1.19v reference, setting the oscil- lator frequency to approximately 220khz. this pin can be driven from an external ac or dc signal source to control the instantaneous frequency of the oscillator. the auxillary boost regulator operates at a constant 1.2mhz frequency. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open, an internal 5v low dropout linear regulator supplies intv cc power. if extv cc is taken above 4.7v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc to intv cc . this allows the intv cc power to be derived from a high efficiency external source such as the output of the regu- lator itself or a secondary winding, as described in appli- cations information. standby mode pin the stbymd pin is a three-state input that controls common circuitry within the ic as follows: when the stbymd pin is held at ground, both controller run/ss pins are pulled to ground providing a single control pin to shut down both controllers. when the pin is left open, the internal run/ss currents are enabled to charge the run/ss capacitor(s), allowing the turn-on of either con- troller and activating necessary common internal biasing. when the stbymd pin is taken above 2v, both internal linear regulators are turned on independent of the state of the two switching regulator controllers, providing output power to wake-up other circuitry. decouple the pin with a small capacitor (0.01 m f) to ground if the pin is not connected to a dc potential. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>7.5%) as well as other more serious condi- tions that may overvoltage the output. in this case, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. power good (pgood) pin the pgood pin is connected to an open drain of an internal mosfet. the mosfet turns on and pulls the pin low when both the outputs are not within 7.5% of their nominal output levels as determined by their resistive feedback dividers. when both controller outputs meet the 7.5% requirement, the mosfet is turned off within 10 m s and the pin is allowed to be pulled up by an external resistor to a source of up to 7v. the auxiliary regulators output is not monitored. foldback current, short-circuit detection and short- circuit latchoff the run/ss capacitors are used initially to limit the inrush current of each step-down switching regulator. after the (refer to functional diagram) operatio u
ltc1876 13 1876fa controller has been started and been given adequate time to charge up the output capacitors and provide full-load current, the run/ss capacitor is used as a short-circuit time-out circuit. if the output voltage falls to less than 70% of its nominal output voltage, the run/ss capacitor be- gins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. if the condition lasts for a long enough period as determined by the size of the run/ss capacitor, both controllers will be shut down until the run/ss pin(s) voltage(s) are recycled. this built- in latchoff can be overridden by providing a >5 m a pull-up at a compliance of 5v to the run/ss pin(s). this current shortens the soft start period but also prevents net dis- charge of the run/ss capacitor(s) during an overcurrent and/or short-circuit condition. foldback current limiting is also activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. even if a short is present and the short- circuit latchoff is not enabled, a safe, low output current is provided due to internal current foldback and actual power wasted is low due to the efficient nature of the current mode switching regulator. theory and benefits of 2-phase operation the ltc1876 dual high efficiency dc/dc controller brings the considerable benefits of 2-phase operation to portable applications for the first time. notebook computers, pdas, handheld terminals and automotive electronics will all benefit from the lower input filtering requirement, reduced electromagnetic interference (emi) and increased effi- ciency associated with 2-phase operation. why the need for 2-phase operation? in most dual con- stant-frequency switching regulators, both regulators are operated in phase (i.e., single-phase operation). this means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capaci- tor and battery. these large amplitude current pulses increased the total rms current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both emi and losses in the input capacitor and battery. with 2-phase operation, the two channels of the dual- switching regulator are operated 180 degrees out of phase. this effectively interleaves the current pulses coming from the switches, greatly reducing the overlap time where they add together. the result is a significant reduction in total rms input current, which in turn allows less expensive input capacitors to be used, reduces shield- ing requirements for emi and improves real world operat- ing efficiency. figure 3 compares the input waveforms for a representa- tive single-phase dual switching regulator to the ltc1876 2-phase dual switching regulator. an actual measurement of the rms input current under these conditions shows that 2-phase operation dropped the input current from 2.53a rms to 1.55a rms . while this is an impressive reduc- tion in itself, remember that the power losses are propor- tional to i rms 2 , meaning that the actual power wasted is reduced by a factor of 2.66. the reduced input ripple voltage also means less power is lost in the input power (refer to functional diagram) operatio u figure 3. input waveforms comparing single-phase (a) and 2-phase (b) operation for dual switching regulators converting 12v to 5v and 3.3v at 3a each. the reduced input ripple with the ltc1876 2-phase regulator allows less expensive input capacitors, reduces shielding requirements for emi and improves efficiency i in(meas) = 2.53a rms (a) single-phase i in(meas) = 1.55a rms (b) 2-phase 5v switch 20v/div 1876 f03a 1876 f03b 3.3v switch 20v/div input current 5a/div input voltage 500mv/div 5v switch 20v/div 3.3v switch 20v/div input current 5a/div input voltage 500mv/div
ltc1876 14 1876fa path, which could include batteries, switches, trace/con- nector resistances and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. of course, the improvement afforded by 2-phase opera- tion is a function of the dual switching regulators relative duty cycles which, in turn, are dependent upon the input voltage v in (duty cycle = v out /v in ). figure 4 shows how the rms input current varies for single-phase and 2-phase operation for 3.3v and 5v regulators over a wide input voltage range. it can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, but in fact extend over a wide region. a good rule of thumb for most applications is that 2-phase operation will reduce allowing a margin for variations in the ltc1876 and external component values yields: r mv i sense max = 50 figure 4. rms input current comparison (refer to functional diagram) operatio u applicatio s i for atio wu u u figure 1 on the first page is a basic ltc1876 application circuit. for the step-down regulators, the external compo- nent selection is driven by the load requirement, and begins with the selection of r sense . once r sense is known, l can be chosen. next, the power mosfets and d1 are selected. finally, c in and c out are selected . the circuit shown in figure 1 can be configured for operation up to an input voltage of 28v (limited by the external mosfets). for the step-up regulator, its component selection is much simpler. a 4.7 m h or 10 m h inductor that can handle at least 1a without saturating will work well with most design. a shottky diode is recommended and a mbr0520 from on semiconductor is a very good choice. r sense selection for output current r sense is chosen based on the required output current. the ltc1876 current comparator has a maximum thresh- old of 75mv/r sense and an input common mode range of sgnd to 1.1(intv cc ). the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, d i l . input voltage (v) 0 input rms current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 10 20 30 40 1876 f04 single phase dual controller 2-phase dual controller v o1 = 5v/3a v o2 = 3.3v/3a the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. operating frequency (khz) 120 170 220 270 320 freqset pin voltage (v) 1876 f05 2.5 2.0 1.5 1.0 0.5 0 figure 5. freqset pin voltage vs frequency
ltc1876 15 1876fa selection of operating frequency the ltc1876 uses a constant frequency architecture with the frequency determined by an internal oscillator capacitor. this internal capacitor is charged by a fixed current plus an additional current that is proportional to the voltage applied to the freqset pin. a graph for the voltage applied to the freqset pin vs frequency is given in figure 5. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum switching frequency is approximately 310khz. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current d i l decreases with higher induc- tance or frequency and increases with higher v in or v out : d i fl v v v l out out in = ? ? ? ? 1 1 ()( ) accepting larger values of d i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is d i l =0.3(i max ). remember, the maximum d i l occurs at the maximum input voltage. the inductor value also has secondary effects. the transi- tion to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher d i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will in- crease. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m m . toroids are very space efficient, especially when you can use several layers of wire. be- cause they generally lack a bobbin, mounting is more difficult. however, designs for surface mount are available that do not increase the height significantly. power mosfet and d1 selection two external power mosfets must be selected for each controller with the ltc1876: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc volt- age. this voltage is typically 5v during start-up (see extv cc pin connection). consequently, logic-level thresh- old mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); applicatio s i for atio wu u u kool m m is a registered trademark of magnetics, inc.
ltc1876 16 1876fa then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss specifi- cation for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , reverse transfer capacitance c rss , input voltage and maximum output current. when the ltc1876 is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v out in = synchronous switch duty cycle vv v in out in = the mosfet power dissipations at maximum output current are given by: p v v ir kv i c f main out in max ds on in max rss = () + () + ()( )( )() 2 2 1 d () p vv v ir sync in out in max ds on = () + () () 2 1 d where d is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mos- fet characteristics. the constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. the schottky diode d1 shown in figure 1 conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead- time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. c in selection the selection of c in is simplified by the multiphase archi- tecture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst case rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms current requirement. increasing the output current, drawn from the other out-of-phase controller, will actually decrease the rms ripple current from this maximum value (see figure 4). the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. the type of input capacitor, value and esr rating have efficiency effects that need to be considered in the selec- tion process. the capacitance value chosen should be sufficient to store adequate charge to keep high peak battery currents down. 20 m f to 40 m f is usually sufficient for a 25w output supply operating at 200khz. the esr of the capacitor is important for capacitor power dissipation as well as overall battery efficiency. all of the power (rms ripple current ? esr) not only heats up the capacitor but wastes power from the battery. applicatio s i for atio wu u u
ltc1876 17 1876fa medium voltage (20v to 35v) ceramic, tantalum, os-con and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramic voltage coefficients are very high and may have audible piezoelec- tric effects; tantalums need to be surge-rated; os-cons suffer from higher inductance, larger case size and limited surface-mount applicability; electrolytics higher esr and dryout possibility require several to be used. multiphase systems allow the lowest amount of capacitance overall. as little as one 22 m f or two to three 10 m f ceramic capaci- tors are an ideal choice in a 20w to 35w power supply due to their extremely low esr. even though the capacitance at 20v is substantially below their rating at zero-bias, very low esr loss makes ceramics an ideal candidate for highest efficiency battery operated systems. also con- sider parallel ceramic and high quality electrolytic capaci- tors as an effective means of achieving esr and bulk capacitance goals. in continuous mode, the source current of the top n-chan- nel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c quired i i vvv v in rms max out in out in re / ? - () [] 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. the benefit of the ltc1876 multiphase controllers can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switch on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. remember that protection fuse resistance, battery resistance and pc board trace resis- tance losses are also reduced due to the reduced peak currents in a multiphase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. the drains of the two top mosfets should be placed within 1cm of each other and share a common c in (s). separating the drains and c in may pro- duce undesirable voltage and current resonances at v in . for the boost regulator, the ripple requirement for the input capacitor is less stringent. if the supply to the regulator is obtained from one of the ltc1876 step-down outputs, a 1 m f to 4.7 m f ceramic capacitor is sufficient. however, if the step-down output is within close proximity (< 1cm) to the boost supply input, there is no need for the capacitor. c out selection the selection of c out is driven by the required effective series resistance (esr). typically once the esr require- ment is satisfied the capacitance is adequate for filtering. for the step-down regulators, the output ripple ( d v out ) is determined by: dd v i esr fc out l out ?+ ? ? ? ? 1 8 where f = operating frequency, c out = output capacitance, and d l = ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. with d i l = 0.4i out(max) the output ripple will typically be less than 50mv at max v in assum- ing: c out recommended esr < 2 r sense and c out > 1/(8fr sense ) the first condition relates to the ripple current into the esr of the output capacitance while the second term guaran- tees that the output capacitance does not significantly applicatio s i for atio wu u u
ltc1876 18 1876fa discharge during the operating frequency period due to ripple current. the choice of using smaller output capaci- tance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage at or below 50mv. the i th pin opti-loop compensation compo- nents can be optimized to provide stable, high perfor- mance transient response regardless of the output capacitors selected. for the boost regulator, the output ripple ( d v out ) is determined by: d v i esr i fc out pk out out ?+ ? ? ? ? 15 . since the boost regulator is operating at high frequency, the second term will be small even with a small value of c out . hence, all efforts can be concentrated on finding a low esr capacitor. a ceramic capacitor can be used for the output capacitor. manufacturers such as nichicon, united chemicon and sanyo can be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest (esr) (size) product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recommended to reduce the inductance effects. in surface mount applications multiple capacitors may need to be used in parallel to meet the esr, rms current handling and load step requirements of the application. aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. spe- cial polymer surface mount capacitors offer very low esr but have lower storage capacity per unit volume than other capacitor types. these capacitors offer a very cost-effec- tive output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. several excellent surge-tested choices are the avx tps, avx tpsv or the kemet t510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors can be used in cost-driven applica- tions providing that consideration is given to ripple current ratings, temperature and long term reliability. a typical application will require several to many aluminum electro- lytic capacitors in parallel. a combination of the above mentioned capacitors will often result in maximizing per- formance and minimizing overall cost. other capacitor types include nichicon pl series, nec neocap, pansonic sp and sprague 595d series. for high value of ceramic capacitors, taiyo yuden has a series of them. select the x5r or x7r series as these retain the capacitance over wide voltage and temperature range. consult manufactur- ers for other specific recommendations. intv cc regulator an internal p-channel low dropout regulator produces 5v at the intv cc pin from the v in supply pin. intv cc powers the drivers and internal circuitry within the ltc1876 step- down controllers. the intv cc pin regulator can supply a peak current of 50ma and must be bypassed to ground with a minimum of 4.7 m f tantalum, 10 m f special polymer, or low esr type electrolytic capacitor. a 1 m f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypassing is neces- sary to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between channels. higher input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc1876 to be exceeded. the system supply current is normally domi- nated by the gate charge current. additional external loading of the intv cc and 3.3v linear regulators also needs to be taken into account for the power dissipation calculations. the total intv cc current can be supplied by either the 5v internal linear regulator or by the extv cc input pin. when the voltage applied to the extv cc pin is less than 4.7v, all of the intv cc current is supplied by the internal 5v linear regulator. power dissipation for the ic in this case is highest: (v in )(i intvcc ), and overall efficiency is lowered. the gate charge current is dependent on applicatio s i for atio wu u u
ltc1876 19 1876fa operating frequency as discussed in the efficiency consid- erations section. the junction temperature can be esti- mated by using the equations given in note 3 of the electrical characteristics. for example, the ltc1876 v in current is limited to less than 24ma from a 24v supply when not using the extv cc pin as follows: t j = 70 c + (24ma)(24v)(95 c/w) = 125 c use of the extv cc input pin reduces the junction tempera- ture to: t j = 70 c + (24ma)(5v)(95 c/w) = 81 c dissipation should be calculated and added for current drawn from the internal 3.3v linear regulator. to prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in con- tinuous mode at maximum v in . extv cc connection the ltc1876 contains an internal p-channel mosfet switch connected between the extv cc and intv cc pins. when the voltage applied to extv cc rises above 4.7v, the internal regulator is turned off and the switch closes, connecting the extv cc pin to the intv cc pin thereby supplying internal power. the switch remains closed as long as the voltage applied to extv cc remains above 4.5v. this allows the mosfet driver and control power to be derived from the output during normal operation (4.7v < v out < 7v) and from the internal regulator when the output is out of regulation (start-up, short-circuit). if more cur- rent is required through the extv cc switch than is speci- fied, an external schottky diode can be added between the extv cc and intv cc pins. do not apply greater than 7v to the extv cc pin and ensure that extv cc < v in . significant efficiency gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of ((duty cycle)/efficiency). for 5v regulators this supply means connecting the extv cc pin directly to v out . however, for 3.3v and other lower voltage regulators, additional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc . make sure the voltage applied to the extv cc does not exceed 7v . 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest efficiency. 3. extv cc connected to the output of the boost regulator. if the ltc1876 auxillary boost regulator is set up for output voltage between 4.7v and 7v, the extv cc can be connected to this output. 4. extv cc connected to an output-derived boost net- work. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. this can be done with either the inductive boost winding as shown in figure 6a or the capacitive charge pump shown in figure 6b. the charge pump has the advantage of simple magnetics. 5. extv cc connected to an external supply. if an external supply is available in the 5v to 7v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. applicatio s i for atio wu u u extv cc fcb sgnd v in tg1 sw bg1 pgnd ltc1876 r sense v out v sec + c out + 1 f 1876 f06a n-ch n-ch r6 + c in v in t1 1:n optional extv cc connection 5v < v sec < 7v r5 figure 6a. secondary output loop and extv cc connection
ltc1876 20 1876fa topside mosfet driver supply (c b , d b ) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mos- fets. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. output voltage the ltc1876 output voltages are each set by an external feedback resistive divider carefully placed across the output capacitor as shown in figure 2. for the step-down controller, the resultant feedback signal is compared with the internal precision 0.8v voltage reference by the error amplifier. the output voltage is given by the equation: vv r r out =+ ? ? ? ? 08 1 2 1 . for the auxillary boost regulator, the resultant feedback signal is compared with the internal precision 1.26v voltage reference by the error amplifier. the output volt- age is given by the equation: vv r r outaux =+ ? ? ? ? 126 1 8 7 . sense + /sense C pins the common mode input range of the current comparator sense pins is from 0v to (1.1)intv cc . continuous linear operation is guaranteed throughout this range allowing output voltage setting from 0.8v to 7.7v, depending upon the voltage applied to extv cc . a differential npn input stage is biased with internal resistors from an internal 2.4v source as shown in the functional diagram. this requires that current either be sourced or sunk from the sense pins depending on the output voltage. if the output voltage is below 2.4v current will flow out of both sense pins to the main output. the output can be easily preloaded by the v out resistive divider to compensate for the current comparators negative input bias current. the maximum current flowing out of each pair of sense pins is: i sense + + i sense C = (2.4v C v out )/24k since v osense is servoed to the 0.8v reference voltage, we can choose r1 in figure 2 to have a maximum value to absorb this current. rk v vv max out 124 08 24 () . . = ? ? ? ? for v out < 2.4v regulating an output voltage of 1.8v, the minimum value of r1 should be 32k. note that for an output voltage above 2.4v, r1 has no maximum value since the sense pins load the output. applicatio s i for atio wu u u extv cc v in tg1 sw bg1 pgnd ltc1876 r sense v out vn2222ll + c out 1876 f06b n-ch n-ch + c in + 1 f v in l1 bat85 bat85 bat85 0.22 f figure 6b. capacitive charge pump for extv cc
ltc1876 21 1876fa soft-start/run function the run/ss1 and run/ss2 pins are multipurpose pins that provide a soft-start function and a means to shut down the ltc1876 step-down controllers. soft-start re- duces the input power sources surge currents by gradu- ally increasing the controllers current limit (proportional to v ith ). this pin can also be used for power supply sequencing. an internal 1.2 m a current source charges up the c ss capacitor . when the voltage on run/ss1 (run/ss2) reaches 1.5v, the particular controller is permitted to start operating. as the voltage on run/ss increases from 1.3v to 3.0v, the internal current limit is increased from 25mv/ r sense to 75mv/r sense . the output current limit ramps up slowly, taking an additional 1.2s/ m f to reach full cur- rent. the output current thus ramps up slowly, reducing the starting surge current required from the input power supply. if run/ss has been pulled all the way to ground there is a delay before starting of approximately: t v a csfc delay ss ss = m =m () 15 12 125 . . ./ t vv a csfc iramp ss ss = - m =m () 315 12 125 . . ./ by pulling both run/ss pins below 1.0v and/or pulling the stbymd pin below 0.2v, the controllers are put into low current shutdown (i q = 20 m a). the run/ss pins can be driven directly from logic as shown in figure 7. diode d1 in figure 7 reduces the start delay but allows c ss to ramp up slowly providing the soft-start function. each run/ss pin has an internal 6v zener clamp (see functional dia- gram). fault conditions: overcurrent latchoff the run/ss pins also provide the ability to latch off the controller(s) when an overcurrent condition is detected. the run/ss capacitor, c ss , is used initially to turn on and limit the inrush current of the controller. after the control- ler has been started and been given adequate time to charge up the output capacitor and provide full load current, the run/ss capacitor is used for a short-circuit timer. if the regulators output voltage falls to less than 70% of its nominal value after c ss reaches 4.1v, c ss begins discharging on the assumption that the output is in an overcurrent condition. if the condition lasts for a long enough period as determined by the size of the c ss and the specified discharge current, the controller will be shut down until the run/ss pin voltage is recycled. if the overload occurs during start-up, the time can be approxi- mated by: t lo1 @ [c ss (4.1 C 1.5 + 4.1 C 3.5)]/(1.2 m a) = 2.7 ? 10 6 (c ss ) if the overload occurs after start-up the voltage on c ss will begin discharging from the zener clamp voltage: t lo2 @ [c ss (6 C 3.5)]/(1.2 m a) = 2.1 ? 10 6 (c ss ) if an overload occurs on one channel, it will also latch off the other channel. this built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the run/ss pin as shown in figure 7. this resistance shortens the soft- start period and prevents the discharge of the run/ss capacitor during an over current condition. tying this pull- up resistor to v in as in figure 7a, defeats overcurrent latchoff. diode-connecting this pull-up resistor to intv cc , as in figure 7b, eliminates any extra supply current during controller shutdown while eliminating the intv cc loading from preventing controller start-up. why should you defeat overcurrent latchoff? during the prototype stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. defeating this feature will easily allow trouble- shooting of the circuit and pc layout. the internal short- circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. after the design is complete, a decision can be made whether to enable the latchoff feature. applicatio s i for atio wu u u figure 7. run/ss pin interfacing 3.3v or 5v run/ss v in intv cc run/ss d1 c ss r ss * c ss r ss * 1876 f07 (a) (b) *optional to defeat overcurrent latchoff
ltc1876 22 1876fa the value of the soft-start capacitor c ss may need to be scaled with output voltage, output capacitance and load current characteristics. the minimum soft-start capaci- tance is given by: c ss > (c out )(v out ) (10 C4 ) (r sense ) the minimum recommended soft-start capacitor of c ss = 0.1 m f will be sufficient for most applications. fault conditions: current limit and current foldback the ltc1876 step-down controllers current comparator has a maximum sense voltage of 75mv resulting in a maximum mosfet current of 75mv/r sense . the maxi- mum value of current limit generally occurs with the largest v in at the highest ambient temperature, conditions that cause the highest power dissipation in the top mosfet. the controllers include current foldback to help further limit load current when the output is shorted to ground. the foldback circuit is active even when the overload shutdown latch described above is overridden. if the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 75mv to 25mv. under short-circuit conditions with very low duty cycles, the step-down regulators will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short- circuit ripple current is determined by the minimum on- time t on(min) (less than 200ns), the input voltage and inductor value: d i l(sc) = t on(min) (v in /l) the resulting short-circuit current is: i mv r i sc sense lsc =+ 25 1 2 d () fault conditions: overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the step-down regulator rises much higher than nominal levels. the crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the controller is operating. a comparator monitors the output for overvoltage condi- tions. the comparator (ov) detects overvoltage faults greater than 7.5% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvolt- age condition is cleared. the output of this comparator is only latched by the overvoltage condition itself and will therefore allow a switching regulator system having a poor pc layout to function while the design is being debugged. the bottom mosfet remains on continuously for as long as the ov condition persists; if v out returns to safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regu- late properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. the standby mode (stbymd) pin function the standby mode (stbymd) pin provides several choices for start-up and standby operational modes. if the pin is pulled to ground, the run/ss pins for both controllers are internally pulled to ground, preventing start-up and thereby providing a single control pin for turning off both control- lers at once. if the pin is left open or decoupled with a capacitor to ground, the run/ss pins are each internally provided with a starting current enabling external control for turning on each controller independently. if the pin is provided with a current of >3 m a at a voltage greater than 2v, both internal linear regulators (intv cc and 3.3v) will be on even when both controllers are shut down. in this mode, the onboard 3.3v and 5v linear regulators can provide power to keep-alive functions such as a keyboard controller. this pin can also be used as a latching on and/ or latching off power switch if so designed. frequency of operation the ltc1876 stepdown controllers have an internal volt- age controlled oscillator. the frequency of this oscillator can be varied over a 2 to 1 range. the pin is internally self- biased at 1.19v, resulting in a free-running frequency of applicatio s i for atio wu u u
ltc1876 23 1876fa approximately 220khz. the freqset pin can be grounded to lower this frequency to approximately 140khz or tied to the intv cc pin to yield approximately 310khz. the freqset pin may be driven with a voltage from 0 to intv cc to fix or modulate the oscillator frequency as shown in figure 5. minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the step down controller is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on- time limit and care should be taken to ensure that. t v vf on min out in () () < if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for each controller is generally less than 200ns. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 300ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. fcb pin operation the fcb pin can be used to regulate a secondary winding or as a logic level input. continuous operation is forced when the fcb pin drops below 0.8v. during continuous mode, current flows continuously in the transformer pri- mary. the secondary winding(s) draw current only when the bottom, synchronous switch is on. when primary load currents are low and/or the v in /v out ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. forced continuous operation will support secondary windings providing there is sufficient synchronous switch duty factor. thus, the fcb input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. with the loop in continuous mode, the auxiliary outputs may nominally be loaded without regard to the primary output load. the secondary output voltage v sec is normally set as shown in figure 6a by the turns ratio n of the transformer: v sec @ (n + 1) v out however, if the controller goes into burst mode operation and halts switching due to a light primary load current, then v sec will droop. an external resistive divider from v sec to the fcb pin sets a minimum voltage v sec(min) : vv r r sec min () . ?+ ? ? ? ? 08 1 6 5 if v sec drops below this level, the fcb voltage forces temporary continuous switching operation until v sec is again above its minimum. in order to prevent erratic operation if no external connec- tions are made to the fcb pin, the fcb pin has a 0.18 m a internal current source pulling the pin high. include this current when choosing resistor values r5 and r6. the following table summarizes the possible states avail- able on the fcb pin: table 1 fcb pin condition 0v to 0.75v forced continuous (current reversal allowedburst inhibited) 0.85v < v fb < 4.3v minimum peak current induces burst mode operation no current reversal allowed feedback resistors regulating a secondary winding >4.8v burst mode operation disabled constant frequency mode enabled no current reversal allowed no minimum peak current remember that both controllers are temporarily forced into continuous mode when the fcb pin falls below 0.8v. applicatio s i for atio wu u u
ltc1876 24 1876fa voltage positioning voltage positioning can be used to minimize peak-to-peak output voltage excursions under worst-case transient loading conditions. the open loop dc gain of the control loop is reduced depending upon the maximum load step specifications. voltage positioning can be easily added to the ltc1876 by loading the i th pin with a resistive divider having a thevenin equivalent voltage source equal to the midpoint operating voltage of the error amplifier, or 1.2v (see figure 8). the resistive load reduces the dc loop gain while main- taining the linear control range of the error amplifier. the maximum output voltage deviation can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. a complete explanation is included in design solutions 10. (see: www.linear-tech.com) 1. the v in current has two components: the first is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents; the second is the current drawn from the 3.3v linear regulator output. v in current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg =f(q t +q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through the extv cc switch input from an output-derived source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(efficiency). for example, in a 20v to 5v application, 10ma of intv cc current results in approxi- mately 3ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resistor, and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approxi- mately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m w , r l = 50m w , r sense = 10m w and r esr = 40m w (sum of both input and output capacitance losses), then the total resistance is 130m w . this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but applicatio s i for atio wu u u i th r c r t1 intv cc c c 1876 f08 ltc1876 r t2 efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1876 circuits: 1) ltc1876 v in current (in- cluding loading on the 3.3v internal regulator), 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. figure 8. active voltage positioning applied to the ltc1876
ltc1876 25 1876fa quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and only when operating at high input voltages (typically 20v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resis- tance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switch- ing frequency. a 25w supply will typically require a minimum of 20 m f to 40 m f of capacitance having a maxi- mum of 20m w to 50m w of esr. the ltc1876 step-down controllers 2-phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky conduction losses during dead- time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load (esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti- loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response . assuming a pre- dominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to maximize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full-load current having a rise time of 1 m s to 10 m s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual over- all supply performance. a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10 m f capacitor would require a 250 m s rise time, limiting the charging current to about 200ma. applicatio s i for atio wu u u
ltc1876 26 1876fa low v in applications in applications where the input supply is low (<5v), the ltc1876 auxiliary regulator can be used to step-up the input to provide the gate drive to the external mosfets as shown in figure 9. shown in the typical application section of the data sheet is a circuit (3.3v in dual-phase high efficiency power supply) with input supply of 3.3v. the boost section of the ltc1876 is set up to generate 5v and is used to provide the gate drive to the external mosfets. the circuit provides dual outputs, a 2.5v/15a and 1.8v/15a. both drawing power directly from v in . applicatio s i for atio wu u u figure 9. generating the gate drive for low input supply applications figure 10. single output configuration single output/high current applications in applications that demand current much higher than a single stage can supply (>20a), the ltc1876 can be configured as a single output converter. figure 10 shows the block diagram of the configuration. note that the compensation pins (i th1 and i th2 ) of the two channels are connected together, saving a set of passive components. in addition, the output voltage sense pins (v osense1 and v osense2 ) are shorted together, using only one resistor divider to set the output voltage. although the output current requirement is high, the input capacitors ripple current requirement is not much differ- ent compared to the dual outputs circuit. this is attributed to the fact that the current is shared between two channels and an out-of-phase architecture is implemented for the controllers (see theory and benefits of 2-phase operation). auxiliary regulators inductor value calculation since the current limit for the auxiliary regulator is inter- nally set at 1a, it makes the selection of components easier. for the boost regulator, the duty cycle is given by: duty cycle v v in out = 1 since energy is only transferred to the output capacitor(s) during the off-time, the maximum output current that can be supplied by the regulator without losing regulation is: i out = 0.5(2 ? i pk C d i l )(1 C duty cycle) where i pk = peak inductor current and is internally set at 1a. d i l = inductors ripple current with the required ripple current determined, the value of the inductor is: l v duty cycle fi in l = d ( ) ( ) where f = operating frequency (1.2mhz) in most cases, a larger value of inductance is used. this is done to account for component variation. it also lowers the inductor ripple current and results in lower core losses. in addition, lower ripple also translates into lower esr losses in the output capacitors and smaller output voltage ripple. 1876 f09 ltc1876 boost section ltc1876 step-down section auxv in auxsw auxv fb sgnd + external mosfets l1 v in c out r7 r8 d1 input supply 1876 f10 ltc1876 sgnd external mosfets v in v out input supply i th1 i th2 v osense1 v osense2 to sense1 + and sense1 to sense2 + and sense2 l1 l2 r2 r1 r s1 r s2 + c c r c
ltc1876 27 1876fa once the value of l is known, select an inductor that can handle at least 1a without saturating. in addition, ensure that the inductor has a low dcr (copper wire resistance) to minimize i 2 r power losses. auxiliary regulators capacitor selection low esr (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice, as they have extremely low esr and are available in very small packages. x5r dielectrics are preferred, followed by x7r, as these materials retain the capacitance over wide voltage and temperature ranges. a 4.7 m f to 10 m f output capacitor is sufficient for most applications, but systems with very low output current may need only a 1 m f or 2.2 m f output capacitor. solid tantalum or os-con capacitors can be used, but they will occupy more board area than a ceramic and will have a higher esr. always use a capacitor with a sufficient voltage rating. ceramic capacitors also make a good choice for the input decoupling capacitor, and should be placed as close as possible to the auxv in pin. a 1 m f to 4.7 m f input capacitor is sufficient for most applications. table 2 shows a list of several ceramic capacitor manufacturers. consult the manufacturers for detailed information on their entire selection of ceramic parts. table 2. ceramic capacitor manufacturers taiyo yuden (408) 573-4150 www.t-yuden.com avx (803) 448-9411 www.avxcorp.com murata (714) 852-2001 www.murata.com the decision to use either low esr (ceramic) capacitors or higher esr (tantalum or os-con) capacitors can affect the stability of the overall system. the esr of any capaci- tor, along with the capacitance itself, contributes a zero to the system. for the tantalum and os-con capacitors, this zero is located at a lower frequency due to the higher value of the esr, while the zero of a ceramic capacitor is a much higher frequency and can generally be ignored. a phase lead zero can be intentionally introduced by placing a capacitor (c3) in parallel with the resistor (r8) between v out3 and auxv fb as shown in figure 11. the frequency of the zero is determined by the following equation. f rc z = 1 283 p by choosing the appropriate values for the resistor and capacitor, the zero frequency can be designed to slightly improve the phase margin of the overall converter. the typical target value for the zero frequency is between 50khz to 150khz. figure 11. adding a phase lead zero auxiliary regulators diode selection a schottky diode is recommended for use with the auxil- iary regulator. the on semiconductor mbr0520 is a very good choice. where the input to output voltage differential exceeds 20v, use the mbr0530 (a 30v diode). these diodes are rated to handle an average forward current of 0.5a. in applications where the average forward current of the diode exceeds 0.5a, a microsemi ups5817 rated at 1a is recommended. driving auxsd above 10v the maximum voltage allowed on the auxsd pin is 10v. in some applications if the applied voltage on this pin is going to exceed 10v, then a series resistor can be con- nected to this pin. the value for this resistor is given by: r v series auxsd = () ( ) 10 60 10 6 by placing this series resistor, it ensures that the voltage seen by the pin will not exceed 10v. 1876 f11 ltc1876 auxv fb v out3 r8 c3 r7 applicatio s i for atio wu u u
ltc1876 28 1876fa automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. but before you connect, be advised: you are plugging into the supply from hell. the main battery line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-bat- tery. load-dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse-battery is just what it says, while double-battery is a consequence of tow-truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 12 is the most straight forward approach to protect a dc/dc converter from the ravages of an automotive battery line. the series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the ltc1876 step-down controllers have a maximum input voltage of 36v, most applications will be limited to 30v by the mosfet bvdss. applicatio s i for atio wu u u figure 12. automotive application protection design example as a design example for one channel, assume v in = 12v (nominal), v in = 22v(max), v out = 1.8v, i max = 5a, and f = 300khz, r sense can immediately be calculated: r sense = 50mv/5a = 0.01 w tie the freqset pin to the intv cc pin for 300khz opera- tion. assume a 4.7 m h inductor and check the actual value of the ripple current. the following equation is used: d i v fl v v l out out in = ? ? ? ? ()( ) 1 the highest value of the ripple current occurs at the maximum input voltage: d i v khz h v v a l = m ? ? ? ? = 18 300 4 7 1 18 22 117 . (. ) . . the ripple current is 23% of maximum output current, which is below the 30% guideline. this means that a 3.3 m h inductor can be used. increasing the ripple current will also help ensure that the minimum on-time of 200ns is not violated. the minimum on-time occurs at maximum v in : t v vf v v khz ns on min out in max () () . () == = 18 22 300 273 since the output voltage is below 2.4v the output resistive divider will need to be sized to not only set the output voltage but also to absorb the sense pins current. rk v vv k v vv k max out 124 08 24 24 08 24 18 32 () . . . .. = ? ? ? ? = ? ? ? ? = v in 1876 f09 ltc1876 transient voltage suppressor general instrument 1.5ka24a 50a i pk rating 12v
ltc1876 29 1876fa choosing 1% resistors; r1 = 25.5k and r2 = 32.4k yields an output voltage of 1.816v. the power dissipation on the top side mosfet can be easily estimated. choosing a siliconix si4412dy results in; r ds(on) = 0.042 w , c rss = 100pf. at maximum input voltage with t(estimated) = 50 c: p v v cc v a pf khz mw main = () + [] w () + ()()( )( ) = 18 22 5 1 0 005 50 25 0 042 1 7 22 5 100 300 220 2 2 . (. )( ) .. a short-circuit to ground will result in a folded back current of: i mv ns v h a sc = w + m ? ? ? ? = 25 001 1 2 200 22 33 32 . () . . with a typical value of r ds(on) and d = (0.005/ c)(20) = 0.1. the resulting power dissipated in the bottom mosfet is: p vv v a mw sync = ()() w () = 22 1 8 22 32 11 0042 434 2 . ... which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 w for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr ( d i l ) = 0.02 w (1.67a) = 33mv pCp design example for auxiliary regulator assume the requirements are v in = 5v, v out = 12v and i outmax = 300ma. the duty cycle is given by: duty cycle v v in out == 1058 . since the required output current is 300ma, the ripple current of the inductor is calculated to be 0.57a. hence the required inductor is: l v duty cycle fi in l = d ( ) ( ) with the boost regulator operating at 1.2mhz, l = 4.24 m h a 10 m h inductor is selected for the circuit for lower ripple inductor current. since the output current is only 300ma, a 0.5a mbr0520 schottky is selected. the completed circuit along with its efficiency curve is shown in figure 13 and figure 14 respectively. applicatio s i for atio wu u u figure 13. design example schematic figure 14. efficiency curve for design example 1876 f13 ltc1876 auxv in v in3 5v v out3 12v 300ma c in3 2.2 f c out3 4.7 f auxsw auxsd auxv fb sgnd + shdn r8 113k r7 13.3k c3* 10pf l3 10 h c1: taiyo yuden x5r lmk212bj225mg c2: taiyo yuden x5r emk316bj475ml d1: on semiconductor mbr0520 l1: sumida cr43-100 *optional d1 load current (ma) 0 efficiency (%) 300 400 1876 f14 100 200 90 85 80 75 70 65 60 55 50 v in = 3.3v v in = 5v
ltc1876 30 1876fa pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1876. these items are also illustrated graphically in the layout diagram of figure 15. the figure 16 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. check the following in your layout: applicatio s i for atio wu u u 1. are the top n-channel mosfets m1 and m3 located within 1cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. is the ground of the step-down controller kept separate from the ground of the step-up regulator? the regulator ground should join the controller ground at the combined c out (C) plates. within the controller circuitry, are the signal and power grounds kept separate? the controller figure 15. ltc1876 recommended printed circuit layout diagram c b1 c b2 c auxin v pull-up (<7v) c intvcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 + c in d1 m1 m2 m3 m4 d2 + c vin v in r in intv cc 3.3v r4 r3 r7 r8 r2 r1 run/ss1 sense1 + sense1 v osense1 freqset stbymd fcb i th1 sgnd 3.3v out i th2 v osense2 sense2 sense2 + auxsgnd auxv fb auxsw auxsw pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 auxsd auxv in auxpgnd auxpgnd ltc1876 l1 l2 c out1 v out1 v out2 1876 f15 + c out2 + r sense r sense shutdown v out3 c out3 d3 l3 4 3 2 1 4 3 2 1
ltc1876 31 1876fa signal ground pin and the ground return of c intvcc must return to the combined c out (C) plates. within the regula- tor circuitry, are the signal and power grounds kept separate? the regulator signal ground pin must return to the c auxin (C) plates. 3. does the path formed by the top n-channel mosfet schottky diode (d1, d2) and the c in capacitor have short leads and pc trace lengths? the output capacitor (C) plates should be connected as close as possible to the (C) plates of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. also, the path formed by the auxsw pins, schottky diode (d3) and the c out3 capacitor should have short leads and pc trace lengths. the c auxin capaci- tor (C) plates should be connected as close as possible to figure 16. branch current waveforms the (C) plates of the c out3 (C) plates by placing the capacitors next to each other and away from the d3 loop described above. 4. if the input supply to the boost regulator is obtain from one of the other outputs, is this connection short (< 1cm)? 5. do the ltc1876 v osense and auxv fb pins resistive dividers connect to the (+) plates of its respective c out ? the resistive divider must be connected between the (+) plate of c out and signal ground and a small v osense decoupling capacitor should be as close as possible to the ltc1876 sgnd pin. a feedforward capacitor across r8 can be connected to enhance the transient response of the boost regulator. the r2, r4 and r8 connections should not be along the high current input feeds from the input capacitor(s). applicatio s i for atio wu u u r l1 d1 l1 sw1 r sense1 v out1 c out1 + v in c in r in + r l2 d2 bold lines indicate high, switching current lines. keep lines to a minimum length. l2 sw2 1876 f16 r sense2 v out2 c out2 +
ltc1876 32 1876fa 6. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. 7. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1 m f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 8. keep the switching nodes (sw1, sw2, auxsw), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, espe- cially from the opposites channels voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc1876 and occupy minimum pc trace area. 9. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging start with one regulator on at a time. it is best to first start with one of the step-down regulator and it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be main- tained over the input voltage range down to dropout and until the output load drops below the low current operation thresholdtypically 10% to 20% of the maximum de- signed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb imple- mentation. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. over- compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for their individual performance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current com- parator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. short-circuit testing can be performed to verify proper overcurrent latchoff, or 5 m a can be provided to the run/ss pin(s) by resistors from v in or intv cc (depend- ing upon the stbymd pin programming), to prevent the short-circuit latchoff from occurring. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervolt- age lockout circuit by further lowering v in and monitoring the outputs to verify operation. investigate whether any problems exist only at higher output currents or only at higher input voltages. if prob- lems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are en- countered with high current output loading at lower input voltages, look for inductive coupling between c in , schot- tky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these com- ponents and the sgnd pin of the ic. applicatio s i for atio wu u u
ltc1876 33 1876fa low voltage 3.3v to 1.8v, 2.5v and 5v power supply 4.7 f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 + 33 f 6.3v, sp d1 m1 m2 m3 m4 d2 + v in 3.3v 3.3v out run/ss1 sense1 + sense1 v osense1 freqset stbymd fcb i th1 sgnd 3.3v out i th2 v osense2 sense2 sense2 + auxsgnd auxv fb auxsw auxsw pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 auxsd auxv in auxpgnd auxpgnd ltc1876 l1 2 h l2 2 h 47 f 6.3v sp 47 f 6.3v sp v out1 2.5v 4a v out2 1.8v 5a 1876 ta02 + + r sense 0.008 r sense 0.008 shutdown v out3 5v 400ma 10 f 20v d5 l3, 5.4 h 0.1 f 0.1 f 1 f 1 f 0.1 f 0.01 f 0.01 f 0.1 f 0.1 f pgood 100k d3 d4 10 + 31.6k 10k 20k 1% 20k 1% 42.5k 1% 25k 1% 6.8k 6.8k 1000pf 1000pf 470pf 220pf 220pf 470pf m1, m2, m3, m4: fds6912a l1, l2: sumida cep123-2ro l3: sumida cdrh5d18 d1, d2: mbrm140t3 d3, d4: bat54a d5: mbr0520 10 f 16v 5r 4 3 2 1 4 3 2 1 an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage. applicatio s i for atio wu u u typical applicatio s u
ltc1876 34 1876fa 3.3v in dual-phase high efficiency power supply 10 f 6.3v 1 f 6.3v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 + d1 m1 2 m2 2 m3 2 m4 2 d2 + 3.3v run/ss1 sense1 + sense1 v osense1 freqset stbymd fcb i th1 sgnd 3.3v out i th2 v osense2 sense2 sense2 + auxsgnd auxv fb auxsw auxsw pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 auxsd auxv in auxpgnd auxpgnd ltc1876 l1 0.9 h l2 0.9 h c4 1 f 6.3v c26 1 f 6.3v v out1 2.5v 15a v out2 1.8v 15a 1876 ta04 + r sense 0.003 r sense 0.003 shutdown 10 f 10v d3 l3, 47 h 0.1 f 0.47 f 2.2 f 6.3v 0.47 f 0.01 f 0.01 f 100pf v pull-up (<7v) 100k d4 10 + 30.9k 1% 10.2k 1% 8.06k 1% 8.25k 1% 17.4k 1% 10k 1% 47k 47k 1000pf 1 f 6.3v 1000pf 6800pf 100pf 100pf 6800pf d1, d2: mbrs340t3 d3: cmdsh-3 d4: bat54a v in 3.3v 4 3 2 1 4 3 2 1 1 f 6.3v 1 f 6.3v + c out1 220 f, 4v, 3 c out2 330 f, 2.5v, 3 c in 330 f 6v, 3 l1, l2: sumida cep134-or9 l3: toko fslb2520-470k m1, m2, m3, m4: fds7764a typical applicatio s u
ltc1876 35 1876fa package descriptio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. g36 ssop 0802 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.50 ?13.10* (.492 ?.516) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 2.0 (.079) 0.05 (.002) 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12 g package 36-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640)
ltc1876 36 1876fa part number description comments ltc1625/ltc1775 no r sense tm current mode synchronous step-down controllers burst mode operation, gn-16 ltc1628/ltc1628-pg high efficiency, dual, 2 phase synchronous step-down controllers constant frequency, standby, 5v and 3.3v ldo ltc1708-pg dual, 2 phase synchronous controller with mobile vid control 36v input; v out1 for cpu core voltage; v out2 for memory, chipset i/o ltc1709 2 phase, 5-bit adustable, high efficiency, synchronous step-down controller constant frequency, vid, up to 42a ltc1735 high efficiency synchronous step-down switching regulator output fault protection, gn-16 ltc1736 high efficiency synchronous controller with mobile vid control output fault protection, g-24 ltc1772 sot-23 step-down controller 2.5v v in 9.8v; i out up to 4.5a; 550khz operation for smallest pcb area ltc1778 no r sense wide input range synchronous step-down controller up to 97% efficiency; 4v v in 36v 0.8v v out (0.9)(v in ); input up to 20a ltc3713 low input voltage synchronous step-down controller 1.5v v in , no r sense , standard 5v-logic level mosfets ltc3714 no r sense dc/dc controller for mobile pentium processors supports up to 25a; sense resistor optional ltc3716 2-phase dc/dc controller for mobile pentium processors small, low profile design; supports up to 30a ltc3728 dual, 2-phase 550khz synchronous step-down controller phase-lockable from 250khz to 550khz, 5mm 5mm qfn and ssop-28, 3.5v v in 36v adaptive power and no r sense are trademarks of linear technology corporation. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2000 lt/tp 1002 1k rev a ? printed in usa related parts typical applicatio n u high efficiency triple 5v/ 3.3v/12v power supply 4.7 f 10v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 + 33 f 35v 10 f 35v d1 m1 m2 m3 m4 d2 + 3.3v run/ss1 sense1 + sense1 v osense1 freqset stbymd fcb i th1 sgnd 3.3v out i th2 v osense2 sense2 sense2 + auxsgnd auxv fb auxsw auxsw pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 auxsd auxv in auxpgnd auxpgnd ltc1876 l1 4.6 h l2 4.6 h 47 f 6.3v sp 56 f 4v sp v out1 3.3v 5a v out2 5v 5a 1876 ta03 + + r sense 0.008 r sense 0.008 shutdown v out3 12v 200ma 10 f 20v d5 l3, 10 h 0.1 f 0.1 f 1 f 0.1 f 0.01 f 0.01 f 0.1 f 0.1 f v pull-up (<7v) 100k d3 d4 10 + 86.6k 10.2k 20k 1% 20k 1% 63.4k 1% 105k 1% 6.8k 6.8k 1000pf 1000pf 470pf 220pf 220pf 470pf m1, m2, m3, m4: fds6912a l1, l2: sumida cep123-4r6 l3: toko a920cy-100m d1, d2: mbrm140t3 d3, d4: bat54a d5: cmdsh-3 intv cc v in 5.2v to 28v 4 3 2 1 4 3 2 1

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